Amplifier

ABSTRACT

An amplifier includes differential input transistors, first switches arranged between each gates and source of the differential input transistors, a second switch arranged to turn on/off a current source that gives the bias of the differential input transistors, and a drive circuit arranged to turn off the second switch and turns on the first switches when the current of the current source is not supplied to the differential input transistors.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an amplifier and an image pickupdevice, and more particularly to an amplifier and an image pickup devicein which a power consumed by the amplifier and an electriccharacteristic hardly change while a 1/f noise generated from atransistor that constitutes a circuit is reduced.

2. Related Background Art

FIG. 1 shows a conventional differential amplifier using a MOStransistor. Differential input signal voltages applied to the inverseand non-inverse input terminals which are connected to the respectivegate terminals of MOS transistors M1 and M2, by a differential inputstage that is connected with the respective source terminals of the MOStransistors Ml and M2 are converted into signal currents, and the signalcurrents are transmitted by a current mirror circuit composed of MOStransistors M3 to M10 and are then added to a current that is invertedby a current mirror circuit composed of MOS transistors M11 to M14 at anode A, and then converted into a signal voltage by an impedance and aload resistor accompanied by the node A and finally outputted from anoutput terminal

The largest sources that generate random noises that appears in theoutput terminal 10 of the differential amplifier are the MOS transistorsM1 and M2 that appear to be input transistors from the view point oftransfer function up to the output terminal 10, and the MOS transistorsM1 and M2 generally are a main generation sources of a noise that has alarger spectrum with respect to a lower frequency called “1/f noise”that is classified as one kind of the random noise.

As a means normally used to reduce the 1/f noise, the product (area) ofthe gate lengths L of the MOS transistors M1 and M2 and the gate width Ware made large since the 1/f noise is represented by the followingexpression:

Vn ² =K/(W·L·Cox·f)

Because the electric characteristic of the differential amplifierlargely depends on the dimensions and characteristics of the inputtransistors M1 and M2, the electric characteristics are not normallydesigned in view of the 1/f noise alone, but determined in accordancewith the their trade-off. Therefore, there are many cases in which it isdifficult to change the gate dimensions of the input transistor toreduce the 1/f noises, after the differential amplifier that satisfiesthe required specification has been designed.

FIG. 2 shows a conventional example (of structure) different from thatof FIG. 1, a type called “folded cascode”, which is identical with thatof FIG. 1 except that MOS transistors M3 and M4 function as currentsources, become active loads and transmit signal currents to the outputstage through the common gate stages of the MOS transistors M5 and M6.

As a method of reducing the 1/f noise of the MOS transistor, there aredisclosed “1/f noise reduction of metal-oxide-semiconductor transistorsby cycling from inversion to accumulation” in Applied Physics LettersApr. 15, 1991 p.1664 to p.1667.

This is designed such that the MOS transistor is switched between twostates of on and off to reduce the 1/f noise per se. FIG. 3 shows the1/f noise measurement example in case of the duty cycle 50% (IEEEJournal of Solid-State Circuits, vol35, N07, JULY 2000, “Reducing MOSFET1/f Noise and Power Consumption by Switched Biasing”). In this feature,0V denotes a point at which the voltage of the gate that results in theabove off state is 0V, and the 1/f noise spectrum is further lower thana value obtained by a modulation theory by about 8 db.

When this result is applied to the conventional differential amplifier,a period of time during which the input transistor turns off may occurand thus its output appears to be an intermittent waveform. This isunacceptable because the output of the differential amplifier needs todeal with continuous signals temporarily.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an amplifier in whichan influence of 1/f noise is controlled.

In order to attain the above-mentioned object, according to one aspectof the present invention, there is provided an amplifier comprising:differential input transistors; first switches arranged between eachcontrol electrode and main electrode (e.g., gate and source in the caseof a field-effect transistor) of the differential input transistors; asecond switch arranged to turn on/off a current source that gives a biasof the differential input transistors; and a drive circuit arranged toturn off the second switch and turn on/off the first switches when thecurrent of the current source is not supplied to the differential inputtransistors.

According to an another aspect of the present invention, there isprovided an amplifier comprising:

differential input transistors;

first switches arranged between each control electrode and mainelectrode of the differential input transistors; a capacitor arranged tohold an output signal of the differential input transistors; a secondswitch arranged to electrically connect the differential inputtransistors with the capacitor; and a drive circuit arranged to turn onthe first switches in a state in which the second switch is turned off.

The other objects and features of the present invention will becomeapparent from the following specification and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a conventional differentialamplifier using MOS transistors;

FIG. 2 is a circuit diagram showing a conventional differentialamplifier with a structure different from that of FIG. 1;

FIG. 3 is a characteristic diagram showing the 1/f noise measurementexample in case of the duty cycle of 50%;

FIG. 4 is a circuit diagram showing a differential amplifier inaccordance with a first embodiment of the present invention;

FIG. 5 is a circuit diagram showing a switch and so forth by using MOStransistors in accordance with the first embodiment in more detail;

FIG. 6 is a timing charts of the circuit shown in FIG. 3;

FIG. 7 is a graph showing output waveforms of the circuit shown in FIG.3 through simulation;

FIG. 8 is a circuit diagram showing an embodiment in which the presentinvention is applied to the differential amplifier of the type shown inFIG. 7;

FIG. 9 is a block diagram showing an embodiment in which thedifferential amplifier of the present invention is applied to a solidstate image pickup device;

FIG. 10 is a block diagram showing a case in which a solid state imagepickup element is applied to a video camera in accordance with a thirdembodiment of the present invention;

FIG. 11 is a block diagram showing a case in which a solid state imagepickup element is applied to a still video camera in accordance with thethird embodiment of the present invention;

FIG. 12 is a schematic diagram showing an original image reading devicethat reads an original image;

FIG. 13 is a block diagram showing the electric structure for explaininga control circuit shown in FIG. 12 in detail;

FIG. 14 is a block diagram showing the structure of an image processingunit of the image reading device;

FIG. 15 is a diagram showing the sectional structure of a reader unitand a printer unit in FIG. 14; and

FIG. 16 is a block diagram showing the rough structure of a cameracontrol system.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a description will be given in detail of preferredembodiments of the present invention with reference to the accompanyingdrawings.

FIG. 4 is a circuit diagram showing a differential amplifier inaccordance with a first embodiment of the present invention. Referringto FIG. 4, reference symbols M21 and M22 denote a pair of inputtransistors, and M23 and M24 denote MOS transistors that are activeloads of the input transistors M21 and M22 when switches SW5 and SW6 areon. The MOS transistors M23 and M24 constitute a current mirror circuitin cooperation with MOS transistors M25 and M26 and transmit signalcurrents from the input transistors M21 and M22, and currents of the MOStransistors M25 and M26 are transmitted to MOS transistors M27 and M28that form another current mirror circuit, and the signal currentsfinally reach an output terminal 4 and are converted into signalvoltages by impedance accompanied by the output terminal 4. Referencesymbol CL denotes a load capacitor.

Switches SW3 to SW7 may basically function in the same phase. SwitchesSW1 and SW2 are turned on/off only at a timing when the switches SW3 toSW7 are turned off and the current mirror circuits and so forth do notnormally operate.

In addition, the switches SW1 and SW2 are not turned on in the samephase but turned on in a time division manner and operate in such amanner that the inversion and non-inversion input terminals of adifferential amplifier connected to terminals 2, 3 are notshort-circuited through the switches SW1 and SW2. However, only in thecase where all of the transistor elements have no variation inmanufacture, the circuit structure is completely symmetrical and theinput conversion off-set voltage that occurs between the above inputterminals does not occur any time, the switches SW1 and SW2 may beoperated in the same phase without any problems.

It is preferable that the switching frequencies of the above switchesSW1 to SW7 are set to be twice or more of a band Bw2 of the output stagecomposed of the MOS transistors M25 to M28. In this case, it is possibleto nearly eliminate an influence of the switching noises that appear inthe output terminal 4 of the amplifier due to the above switching.Alternatively, needless to say, a low pass filter having a cut-off lowerthan the switching frequency in accordance with a specification requiredfor the amplifier may be connected to the output terminal 4 to providethe filter output as a final output.

FIG. 5 is a circuit diagram showing the switches and so forth by usingMOS transistors in accordance with the above-mentioned embodiment inmore detail, and the basic structure of the circuit is identical withthe structure of FIG. 1, in which MOS transistors M15 to M19 correspondto the switches SW5, SW6, SW1, SW2 and SW7 in FIG. 4. MOS transistorsM20 and M21′ are transistors that function as current sources, and a MOStransistor M22′ is a voltage source that gives the gate biases of theMOS transistors M11 and M12. The switch SW7 of the MOS transistor M19may be structured as a switch that is not connected in series to thecurrent source M20 but controls the output current per se of the currentsource M20 as shown in FIG. 5. A terminal INN is an inversion inputterminal of the amplifier, and INP is a non-inversion input terminal ofthe amplifier.

FIG. 6 shows a timing of the circuit shown in FIG. 5. In the case wherethe differential amplifier is structured as an inversion amplifier, itis preferable that the MOS transistor M17 (switch SW1) is turned on witha delay from the MOS transistor M18 (switch SW2). This is because theMOS transistor M18 is connected to the non-inversion input terminal,there are normally many cases in which the non-inversion input terminalis connected to a certain power source, and therefore a currentnecessary for raising the source potential of the MOS transistor M18when the MOS transistor M18 is turned on can be supplied from thecurrent source.

FIG. 7 shows an output waveform of the circuit shown in FIG. 5 throughsimulation, in which a top output waveform is a waveform of an outputresulting from conducting the above-mentioned switching operation, amiddle waveform is a waveform of the top waveform from which a switchingnoise is removed through a filter, and a bottom waveform is a waveformof a conventional amplifier that is not subjected to switching.

Because an influence of the switching noise in the top waveform isdetermined in accordance with a relationship among the bands of initialand subsequent stages of the amplifier, the attenuation characteristicsand the switching frequencies, the respective values may be determinedin accordance with the specification required for the amplifier.

In this embodiment, since the hold characteristic of a signal voltage inthe current mirror circuit unit is improved when the switches SW5, SW6and SW7 are turned off, a noise that appears in the output terminal dueto the switching operation of the switches SW1 and SW2 can be reduced,and an influence of the switching operation can be lessened. When onlythe switches SW3 and SW4 are provided, the switching noise that occurswhen the switches SW3 and SW4 are off becomes remarkably large.

In this embodiment, the on/off control of the switches SW is conductedby a drive circuit.

As described above, at the timing when the switches SW1 and SW2 areturned on/off, the differential transistor pair M21 and M22 and thecapacitor CL are not electrically connected to each other. Therefore,the influence of the noise, which is generated due to turning on/off ofthe switches SW1 and SW2, on the signal hold in the capacitor CL isdecreased. As a result, it is possible to obtain a signal with highprecision.

In this case, a structure in which the switches SW3 to SW7 are turnedoff at the timing when the switches SW1 and SW2 are turned on/off, wasdescribed above. The above-mentioned structure allows the influence ofthe noise to be suppressed the most. However, it may employ a structurein which only the switches SW3 and SW4 are provided so as to be turnedoff at the timing when the SW1 and SW2 are turned on/off.

FIG. 8 is a circuit diagram showing an amplifier in accordance with asecond embodiment of the present invention to which the conventionalamplifier of the type shown in FIG. 2 is applied.

Reference symbols I1, I2 and I3 denote constant current source for bias,and the switches SW3 and SW4 function as a common gate stage at the timeof L0 and as switch-off at the time of HI by switching by HI/LO(appropriate VREF voltage) the gate potential of the common gate stagein the conventional example shown in FIG. 1. The switch SW5 is disposedat the output of the current mirror circuit of the MOS transistors M23and M24, and functions as a sample/hold circuit in which a loadcapacitor CL is regarded as a hold capacitor when the switches SW3, SW4and SW5 are off. The switch SW5 may be replaced with control of the gatepotentials of the current mirror circuits M23 and M24.

In case of this embodiment, since there is a tendency to make theswitching noise larger as compared with that of the first embodiment, itis necessary that the cut-off frequency of a low-pass filter connectedto the output terminal 4 is set to a value remarkably lower than theband of the amplifier. In this embodiment, the on/off control of theswitch SW is conducted by a drive circuit.

As described above, at the timing when the switches SW1 and SW2 areturned on/off, the differential transistor pair M21 and M22 and thecapacitor CL are not electrically connected to each other. Therefore,the influence of the noise, which is generated due to turning on/off ofthe switches SW1 and SW2, on the signal hold in the capacitor CL isdecreased. As a result, it is possible to obtain a signal with highprecision.

In this case, a structure in which the switches SW3 to SW6 are turnedoff at the timing when the switches SW1 and SW2 are turned on/off, wasdescribed above. The above-mentioned structure allows the influence ofthe noise to be suppressed the most. However, it may employ a structurein which only the switches SW3 and SW4 are provided so as to be turnedoff at the timing when the SW1 and SW2 are turned on/off.

FIG. 9 shows a case in which the differential amplifier of the first orsecond embodiment is applied to a solid state image pickup element inaccordance with a third embodiment. In this embodiment in the solidstate image pickup element that deals with a video signal, an influenceof the above 1/f noise is normally large, and for the purpose ofreducing the 1/f noise, a noise reducing circuit called “CDS (correlateddouble sampling)” is used. Therefore, a significance for reducing the1/f noise by using the differential amplifier for the solid state imagepickup element is large. Reference numeral 41 denotes sensor cells whichare arranged two-dimensionally as one example. Reference numerals 42-1,42-2, . . . , 42-m denote select signal lines that select rows of thesensor cells. The select signal lines are driven by a vertical shiftregister 48. Reference numerals 43-1, 43-2, . . . , 43-n denote verticalsignal lines, and the signals of the respective sensor cells 41 selectedby the select signal lines 42-1 to 42-m appear in the vertical signallines 43-1 to 43-n. Reference numerals 44-1, 44-2, . . . , 44-n denotehorizontal transfer switches which are driven by a horizontal shiftregister 47, and sequentially read the signal that appear in thevertical signal lines 43-1 to 43-n to a horizontal signal line 45 bysequentially turning on the horizontal transfer switches 44-1 to 44-n.The signal read into the horizontal signal line 45 is amplified by adifferential amplifier 49 of the present invention, and then outputtedfrom an output terminal 50. Switching operation for reducing the 1/fnoise is conducted within the differential amplifier 49 at any time, anda low pass filter may be further connected to the output terminal 10 forthe purpose of suppressing the switching noise.

A fourth embodiment of the present invention in the case where a solidstate image pickup element according to the third embodiment is appliedto the video camera will be described in detail with reference to FIG.10.

Reference numeral 51 denotes a photographing lens that includes a focuslens 51A for adjusting a focal point, a zoom lens 51B that conducts thezoom operation, and an imaging lens 51C. Reference numeral 52 denotes aniris, 53 denotes a solid state image pickup element thatphotoelectrically converts an image of the object which is imaged on aphotographing plane into an electric image pickup signal, and 54 denotesa sample/hold circuit (S/H circuit) that samples and holds the imagepickup signal outputted from the solid-state image pickup element 53 andalso amplifies the level to output the video signal.

Reference numeral 55 denotes a process circuit that subjects the videosignal outputted from the sample/hold circuit 54 to given processes suchas gamma correction, color separation, and blanking processing, tooutput a luminance signal Y and a chroma signal C. The chroma signal Coutputted from the process circuit 55 is subjected to corrections ofwhite balance and color balance by a chrominance signal correctioncircuit 71 and then outputted to an encoder circuit (ENC circuit) 74 anda gate circuit 72 as color difference signals R-Y and B-Y. An output ofthe gate circuit 72 is inputted to an integral circuit 75, and an outputof the integral circuit 75 is inputted to a logical control circuit 67.Also, the luminance signal Y outputted from the process circuit 55 andthe color difference signals R-Y and B-Y outputted from the chrominancesignal correction circuit 71 are modulated by the encoder circuit (ENCcircuit) 74 and then outputted as standard television signals. Then,those signals are supplied to a monitor EVF such as a video recorder oran electronic view finder (not shown). Then, reference numeral 56denotes an iris control circuit that controls the iris drive circuit 57on the basis of the video signal supplied from the sample/hold circuit54 and automatically controls an ig meter 58 to control the openingdegree of the iris 52 so that a level of the video signal becomes afixed value of a given level.

Reference numerals 63 and 64 denote band pass filters (BPFs) havingdifferent band limits which extract high frequency components necessaryto conduct focus detection from the video signals outputted from thesample/hold circuit 54. Signals outputted from the first band passfilter 63 (BPF1) and the second band pass filter 64 (BPF2) are gated bya gate circuit 65 and a focus gate frame signal, respectively, and apeak value is detected and held by a peak detection circuit 66 and alsoinputted to the logical control circuit 67. This signal is called “focalpoint voltage”, and focusing is made by the focal point voltage. Thelogical control circuit 67 is connected to a gate pulse generationcircuit 73, and the gate pulse generation circuit 73 sends pulses to thegate circuits 65 and 72. Also, reference numeral 68 denotes a focusencoder that detects the moving position of the focus lens 51A, 69denotes a zoom encoder that detects the focal point distance of the zoomlens 51B, and 70 denotes an iris encoder that detects the opening degreeof the iris 52. The detected value of the encoder 70 is supplied to thelogical control circuit 67 that conducts system control. The logicalcontrol circuit 67 conducts the focus detection with respect to theobject on the basis of the video signal corresponding within a set focusdetection region to adjust the focal point. That is, the logical controlcircuit 67 takes in the peak value information of the high frequencycomponent supplied from the respective band pass filters 63 and 64, andsupplies control signals of the rotating direction, the rotating speed,the rotation/stop and so forth of a focus motor 60 to a focus drivecircuit 59 so as to drive the focus lens 51A to a position at which thepeak value of the high frequency component becomes maximum, and controlsthe focus drive circuit 59. Also, the logical control circuit 67supplies the control signal of a zoom motor 62 to a zoom drive circuit61 so as to drive the zoom lens 51B and controls the zoom drive circuit.

A fifth embodiment in the case where the solid-state image pickupelement according to the third embodiment is applied to a still camerawill be described in detail with reference to FIG. 11.

Referring to FIG. 11, reference numeral 81 denotes a barrier that servesas the protector of the lens and a main switch, 82 denotes a lens thatforms the optical image of the object onto a solid-state image pickupelement 84, 83 denotes an iris for varying the quantity of light thatpasses through the lens 82, 84 denotes a solid-state image pickupelement for taking in the object image which is formed by the lens 82 asan image signal, 85 denotes an image signal processing circuit thatprocesses the image signal outputted from the solid-state image pickupelement 84, 86 denotes an A/D conversion circuit that conductsanalog/digital conversion of the image signal outputted from the imagesignal processing circuit 85, 87 denotes a signal processing unit thatconducts various corrections on the image data outputted from the A/Dconversion circuit 86 and compresses the data, 88 denotes a timinggeneration unit that outputs various timing signals to the solid-stateimage pickup element 84, the image signal processing circuit 85, the A/Dconversion circuit 86 and the signal processing unit 87, 89 denotes asystem control and operation unit that controls the various calculationsand the entire still video camera, 90 denotes a memory unit fortemporarily storing the image data, 91 denotes an interface unit forconducting recording or reading with respect to the recording medium, 92denotes a detachably attachable recording medium such as a semiconductormemory for conducting the recording or the reading of the image data,and 93 denotes an interface unit for communicating with an externalcomputer or the like.

Subsequently, the operation of the thus-structured still video camerathus structured at the time of photographing will be described. When thebarrier 81 is opened, the main power supply is turned on, andsubsequently, a power supply for the control system is turned on, andalso a power supply for the image pickup system circuit such as the A/Dconversion circuit 86 is turned on. Then, in order to control thequantity of exposure, the system control and operation unit 89 releasesthe iris 83, and the signal outputted from the solid-state image pickupelement 84 is converted by the A/D conversion circuit 86, after passingthrough the image signal processing circuit 85, and then inputted to thesignal processing unit 87. The calculation of the exposure is conductedby the system control and operation unit 89 on the basis of that data.The brightness is judged on the basis of the result of photometry, andthe system control and operation unit 89 controls the iris 83 inaccordance with the result. Then, the system control and operation unit89 extracts the high frequency component and calculates a distance tothe object on the basis of the signal outputted from the solid-stateimage pickup element 84. Thereafter, the system control and operationunit 89 drives the lens 82 to judge whether focusing is made or not, andwhen it is judged that focusing is not made, the lens 82 is again drivento conduct the range finding. Then, after the focusing is recognized,actual exposure starts. After the exposure is completed, the imagesignal outputted from the solid-state image pickup element 84 is A/Dconverted by the A/D conversion circuit 86, after passing through theimage signal processing circuit 85. The A/D converted signal passesthrough the signal processing unit 87 and is then written in the memoryunit 90 by the system control and operation unit 89. Thereafter, thedata stored in the memory unit 90 passes through the recording mediumcontrol I/F unit 91 and is recorded in the detachably attachablerecording medium 92 such as a semiconductor memory under the control ofthe system control and operation unit 89. Also, the data may be inputteddirectly to the computer or the like through an external I/F unit 93 toprocess the image.

A sixth embodiment in the case where the solid-state image pickupelement according to the third embodiment is applied to a sheet-feedtype original image recording deice will be described in detail withreference to FIGS. 12 and 13. FIG. 12 is a schematic diagram showing anoriginal image reading device that reads an original image. Referencenumeral 101 denotes a contact type image sensor (hereinafter also called“CIS”) which is composed of a solid-state image pickup element 102, acell fok lens 103, an LED array 104 and a contact glass 105. Feedrollers 106 are disposed in front of and at the back of the CIS 101, andused for arranging an original. A contact sheet 107 is used to bring theoriginal in contact with the CIS 101. Reference numeral 110 denotes acontrol circuit that processes a signal from the CIS 101. An originaldetection lever 108 is a lever for detecting that the original isinserted thereinto, and when the original detection lever 108 detectsthat the original is inserted, the original detection lever 108 isinclined to change an output of the original detection sensor 109. Then,this state is transmitted to a CPU 215 within the control circuit 110,and it is judged that the original is inserted, and a drive motor of theoriginal feed rollers 106 (not shown) is driven to start the originalfeeding to conduct the reading operation.

FIG. 13 is a block diagram showing an electric structure for explainingthe control circuit 110 shown in FIG. 12 in detail. Hereinafter, thecircuit operation will be described with reference to FIG. 13.

Referring to FIG. 13, reference numeral 201 denotes an image sensor (CIS101 shown in FIG. 12) which is integrated with LEDs 202 of therespective colors R, G and B which are light sources. The image sensor201 can sequentially read the color images of R, G and B lines byswitchingly turning on the LEDs 202 of the respective colors R, G and Bfor each line by an LED control (drive) circuit 203 while the originalis fed on the contact glass 105 of the CIS 101. Reference symbol AMP204denotes an amplifier that amplifies a signal outputted from the CIS 201,and 205 denotes an A/D conversion circuit that A/D converts theamplified output to obtain a digital output of, for example, 8 bits. Ashading RAM 206 stores therein shading correction data by reading acalibration sheet in advance, and a shading correction circuit 207conducts the shading correction of the read image signal read on thebasis of the data of the shading RAM 206. A peak detection circuit 208is a circuit that detects a peak value of the read image data for eachline and is used for detecting a leading edge of the original. A gammaconversion circuit 209 conducts the gamma conversion of the read imagedata in accordance with a gamma curve predetermined by a host computer.A buffer RAM 210 is a RAM for temporarily storing the image data inorder to synchronize timings of the actual reading operation and thehost computer in communication with each other, and a packing/buffer RAMcontrol circuit 211, after conducting a packing process in accordancewith image output modes (binary value, 4-bit multi-value, 8-bitmulti-value, 24-bit multi-value) predetermined by the host computer,writes the data in the buffer RAM 210 and reads the image data in aninterface circuit 212 from the buffer RAM 210 to output the data. Theinterface circuit 212 receives a control signal and also outputs theimage signal with respect to an external apparatus 213 which is the hostdevice of the image reading device of this embodiment, for example, thepersonal computer. Reference numeral 215 denotes, for example, a CPU inthe form of a microcomputer, which includes a ROM 215A that stores aprocessing procedure therein and a RAM 215B for operation, and controlsthe respective units in accordance with the procedure stored in the ROM215A. Reference numeral 216 denotes, for example, a crystal oscillator,214 denotes a timing signal generation circuit that divides the outputof the oscillator 216 in accordance with the setting of the CPU 215 andgenerates various timing signals which are used as references of theoperation. Reference numeral 213 denotes an external apparatus connectedwith the control circuit through the interface circuit 212, and apersonal computer may be cited as an example of the external device.

A seventh embodiment in the case where the solid-state image pickupelement of the third embodiment is applied to an original image readingdevice having a communication function or the like will be described indetail with reference to FIGS. 14 and 15.

FIG. 14 is a block diagram showing the structure of an image processingunit of the image reading device. Referring to FIG. 14, a reader unit301 reads an original image (not shown), and outputs the image datacorresponding to the original image to a printer unit 302 and an imageinput/output control unit 303. The printer unit 302 records the imagecorresponding to the image data from the reader unit 301 and the imageinput/output control unit 303 on a recording sheet.

The image input/output control unit 303 is connected to the reader unit301 and is composed of a facsimile unit 304, a file unit 305, a computerinterface unit 307, a formatter unit 308, an image memory unit 309, acore unit 310 and so forth. Among them, the facsimile unit 304 transfersthe image data resulting from extending the compressed image datareceived through a telephone line 313 to the core unit 310, and alsotransmits a compressed image data resulting from compressing the imagedata transferred from the core unit 310 through the telephone line 313.The facsimile unit 304 is connected with a hard disk 312 so as totemporarily save the received compressed image data. The file unit 305is connected with a magneto-optical disk drive unit 306, and the fileunit 305 compresses the image data transferred from the core unit 310and stores the image data together with a keyword for retrieving theimage data in the magneto-optical disk arranged in the magneto-opticaldisk drive unit 306. Also, the file unit 305 retrieves the compressedimage data stored in the magneto-optical disk on the basis of thekeyword transferred through the core unit 310. Then, the file unit 305reads and extends the retrieved compressed image data and transfers theextended image data to the core unit 310. The computer interface unit307 is an interface between a personal computer or a workstation (PC/WS)311 and the core unit 310. Also, the formatter unit 308 develops codedata that represents the image transferred from the PC/WS 311 to theimage data that can be recorded in the printer unit 302, and the imagememory unit 309 temporarily stores the data transferred from the PW/WS311. The core unit 310 controls the flow of data between the reader unit301, the facsimile unit 304, the file unit 305, the computer interfaceunit 307, the formatter unit 308 and the image memory unit 309.

FIG. 15 is a diagram showing the sectional structures of the reader unit301 and the printer unit 302 shown in FIG. 14. Referring to FIG. 15, anoriginal supply device 401 of the reader unit 301 feeds an original (notshown) onto a platen glass 402 from a last page, one by one in order,and discharges the original on the platen glass 402 after the originalreading operation is completed. Also, when the original is fed onto theplaten glass 402, the reader unit 301 turns on a lamp 403, and startsthe movement of a scanner unit 404 to scan the original with exposure. Areflected light from the original due to the exposure scanning is guidedto a solid-state image pickup element 409 by mirrors 405, 406, 407 and alens 408. In this way, the scanned original image is read by thesolid-state image pickup element 409. The image data outputted from thesolid-state image pickup element 409 is transferred to the printer unit302 or the core unit 310 after being subjected to a process such as A/Dconversion or shading correction.

Laser drivers 521(a) and 521(b) of the printer unit 302 drive laseremitting units 501(a) and 501(b), and cause the laser emitting units501(a) and 501(b) to emit laser beams corresponding to the image dataoutputted from the reader unit 301. The laser beams are irradiated ontodifferent positions of a photosensitive drum 502, and latent imagescorresponding to those laser beams are formed on the photosensitive drum502. A developer is adhered to the portions of the latent images on thephotosensitive drum 502 by developing machine 503(a) and 503(b). Then,the recording sheet is fed from any one of a cassette 504 and a cassette505 at a timing which is in synchronism with the start of the laser beamirradiation, and is transferred to a transfer unit 506 and the developeradhered to the photosensitive drum 502 is transferred onto the recordingsheet. The recording sheet on which the developer is deposited is fedonto a fixing unit 507, and the developer is fixed onto the recordingsheet due to a heat and a pressure in the fixing unit 507. The recordingsheet that has passed through the fixing unit 507 is discharged by adischarge roller 508, and a sorter 520 receives the discharged recordingsheets into the respective pins and sorts the recording sheets. In thecase where sorting is not set, after the sorter 520 feeds the recordingsheet to the discharge roller 508, the sorter 520 reverses the rotatingdirection of the discharge roller 508 and then guides the recordingsheet to a sheet re-feed path 510 by a flapper 509. Also, in the casewhere the multiple recording is not set, the recording sheet is guidedto the sheet re-feed path 510 by the flapper 509 in such a manner thatthe recording sheet is not fed to the discharge roller 508. Therecording sheet guided to the re-feed path 510 is supplied to thetransfer unit 506 at the same timing as the above-mentioned timing.

A camera control system having a video camera of the fourth embodimentusing the solid-state image pickup element of the third embodiment willbe described in detail with reference to FIG. 16 in accordance with aneighth embodiment of the present invention. This embodiment is notlimited to the video camera of the fourth embodiment but may be directedto the still camera of the fifth embodiment using the solid-state imagepickup element of the third embodiment.

FIG. 16 is a block diagram showing the rough structure of a cameracontrol system. Reference numeral 710 denotes a network that transmitsvideo data and camera control information (including status information)in a digital format and is connected with n image transmitting terminals712 (712-1 to 712-n). The respective image transmitting terminals 712(712-1 to 712-n) are connected with video cameras 716 (716-1 to 716-n)through camera control devices 714 (714-1 to 714-n). The camera controldevices 714 (714-1 to 714-n) control the pan, tilt, zoom, focus, irisand the like of the connected video cameras 716 (716-1 to 716-n) inaccordance with the control signals from the image transmittingterminals 712 and the video cameras 716 (716-1 to 716-n). Also, thevideo cameras 716 (716-1 to 716-n) are applied with power supply fromthe camera control devices 714 (714-1 to 714-n), and the camera controldevices 714 (714-1 to 714-n) control the on/off operation of the powersupply of the video cameras 716 (716-1 to 716-n) in accordance with anexternal control signal. Also, the network 710 is connected with imagereception terminals 718 (718-1 to 718-m) that receive the imageinformation sent from the image transmitting terminals 712 (712-1 to712-n) to the network 710 and display the image information. Therespective image reception terminals 718 (718-1 to 718-m) are connectedwith monitors 720 (720-1 to 720-m) each composed of a bit map display, aCRT or the like. In this example, the network 710 does not need to bewired, but may be a wireless network using a wireless LAN device. Inthis case, the image reception terminal 718 may be a portable imagereception terminal device integrated with the monitor 720. The imagetransmitting terminals 712 (712-1 to 712-n) compress the output videosignals of the connected video cameras 716 (716-1 to 716-n) by givencompression systems such as H.261 or the like and transmit thecompressed video signals to an image requesting image reception terminal718 or all of the image reception terminals 718. The image receptionterminals 718 can control the on/off operation of the power supplytogether with various parameters (photograph orientation, photographmagnification, focus, iris, etc.) of an arbitrary camera 716 through thenetwork 710, the image transmitting terminals 712 and the camera controldevice 714. In this example, the image transmitting terminal 712 may beconnected with a monitor and provided with an image extension devicethat extends the compression image so as to also serve as the imagereception terminal. On the other hand, the image reception terminals 718may be connected with the camera control devices 714 and the videocameras 716 and provided with the image compression devices so as toalso function as the image transmitting terminals. Those terminals areprovided with ROMs that store software necessary to transmit or receivethe image.

With the above structure, the image transmitting terminals 712 transmitthe video signals to the image reception terminals 718 that is at aremote location through the network 710, and receive the camera controlsignals transmitted from the image reception terminals 718 to executethe control of the pan, tilt and so forth of the video cameras 716.Also, the image reception terminals 718 send the camera control signalsto the image transmitting terminals 712, and the image transmittingterminals 712 that receive the camera control signals control the videocameras 716 in accordance with the contents of the camera control signaland return the present status of the video cameras 716. The imagereception terminals 718 receive the video data transmitted from theimage transmitting terminals 712 and perform a predetermined processingon the video data to display the picked-up image on the display screensof the monitor 720 in real time.

As was described above, the connection of the control electrode and themain electrode of the input transistor which is a main 1/f noise sourcein the amplifier is turned on/off by the switch, and the switching noisethat appears in the output of the differential amplifier due to theabove switching is more reduced while the 1/f noise per se of the inputtransistor is reduced with the advantages in that a change in theelectric characteristic of the differential amplifier, the powerconsumption, an increase in the size of the input transistor, and so onare eliminated.

The foregoing description of the preferred embodiments of the inventionhas been presented for purposes of illustration and description. It isnot intended to be exhaustive or to limit the invention to the preciseform disclosed, and modifications and variations thereof are possible inlight of the above teachings or may be acquired from practice of theinvention. The embodiments were chosen and described in order to explainthe principles of the invention and its practical application enablesone skilled in the art to utilize the invention in various embodimentsand with various modifications as are suited to the particular usecontemplated. It is intended that the scope of the invention be definedby the claims appended hereto, and their equivalents.

What is claimed is:
 1. An amplifier comprising: differential inputtransistors; first switches arranged between each control electrode andmain electrode of said differential input transistors; a second switcharranged to turn on/off current source that gives a bias of saiddifferential input transistors; and a drive circuit arranged to turn onsaid first switches when said second switch is turned off and thecurrent of said current source is not supplied to said differentialinput transistors.
 2. An amplifier according to claim 1, wherein saiddrive circuit prevents overlap of timings at which the first switcheswhich are disposed between the respective control electrodes and therespective main electrodes of said differential input transistors areturned on.
 3. An amplifier according to claim 1, further comprising acurrent mirror circuit arranged to function as an active load of saiddifferential input transistors, and a third switch arranged in a signalcurrent path for outputting the output signal of said differential inputtransistors to said current mirror circuit, wherein said drive circuitturns on said first switches at a timing where said second and thirdswitches are turned off.
 4. An amplifier according to claim 3, whereinsaid third switch controls gate potential of a common gate circuit thatis connected to the output terminals of said differential inputtransistors.
 5. An amplifier according to claim 3, further comprising afourth switch arranged between the control electrode and the mainelectrode of the transistor that constitutes said current mirror circuitwhich is the active load; wherein said drive circuit turns on said firstswitches at a timing where said second to fourth switches are turnedoff.
 6. An image pickup apparatus comprising: a plurality of sensorcells; a common output line to which signals are outputted sequentiallyfrom said plurality of sensor cells; and an amplifier as claimed inclaim 1, arranged to amplify and output sequential signals from saidcommon output line.
 7. An image pickup apparatus according to claim 6,further comprising an optical system arranged to form light into anoptical image on said plurality of sensor cells, and a signal processingcircuit arranged to process a signal from said amplifier.
 8. Anamplifier comprising: differential input transistors; first switchesarranged between each control electrode and main electrode of saiddifferential input transistors; a capacitor arranged to hold an outputsignal of said differential input transistors; a second switch arrangedto electrically connect said differential input transistors with saidcapacitor; and a drive circuit arranged to turn on said first switchesin a state in which said second switch is turned off.
 9. An image pickupapparatus comprising: a plurality of sensor cells; a common output lineto which signals are outputted sequentially from said plurality ofsensor cells; and an amplifier as claimed in claim 8, arranged toamplify and output sequential signals from said common output line. 10.An apparatus according to claim 9, further comprising: an optical systemarranged to form light into an optical image on said plurality of sensorcells; and a signal processing circuit arranged to process a signal fromsaid amplifier.